Complementary metal-oxide semiconductors (CMOS), are a major class of integrated circuits (IC). CMOS chips include microprocessors, microcontrollers, static RAM, and other digital logic circuits and RF/analog circuits.
Generally CMOS processing includes forming multiple shallow trench isolation (STI) regions in a top layer of a substrate. The STI regions are typically formed so as to isolate, for example, a device region in a silicon on insulator (SOI) or bulk substrate, from another device region. A plurality of wells, e.g. p-wells, n-wells, can also be formed in the device region. For example, a p-well is formed of p-type semiconductor material, and an n-well is formed of n-type semiconductor material. The p-well and n-well regions are formed utilizing processing steps that are known to those skilled in the art including, for example, trench definition and etching, optionally lining the trench with a diffusion barrier, and filling the trench with a trench dielectric such as an oxide. After the trench fill, the structure may be planarized and an optional densification process step may be performed to densify the trench dielectric.
More specifically, the device region is processed utilizing conventional block mask techniques. A block mask that can be used in forming a device region can comprise a conventional soft and/or hard mask material and it can be formed using deposition, photolithography and etching. For example, the block mask can comprise a photoresist. A photoresist block mask can be produced by applying a blanket photoresist layer to the substrate surface, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing conventional resist developer.
Alternatively, the block mask can be a hard mask material. Hard mask materials include dielectrics that may be deposited by chemical vapor deposition (CVD) and related methods. Typically, the hard mask composition includes silicon oxides, silicon carbides, silicon nitrides, silicon carbonitrides, etc. Spin-on dielectrics may also be utilized as a hard mask material including but not limited to: silsesquioxanes, siloxanes, and boron phosphate silicate glass (BPSG).
An device region (wells) may be formed by selectively implanting p-type or n-type dopants into the semiconductor layer. It is noted that the n-type device region is typically used when a pFET channel is to be subsequently formed, while a p-type device region is typically used when an nFET channel is to be subsequently formed.
In the state of the art complementary metal-oxide semiconductor (CMOS) technologies, shallow trench isolation induces stress in a channel area of a device region which in most cases degrades the drive current. A cause of performance degradation of the drive current is the mobility degradation due to local stress. The amount of stress is sensitive to the size of the device region and the distance between the channel and a shallow trench isolation (STI) edge, in other words, sensitive to the device layout. In addition, the stress induced by STI is a component of undesirable narrow width effect. Currently, various oxides and nitrides are used on STI regions. However, for example, oxide, nitride and silicon, have different thermal expansion coefficients, and thus it is difficult to control the stress or minimize the harmful stress.
It would therefore be desirable to enhance performance of a CMOS chip/wafer and also reduce the process-induced variations without significantly increasing the cost of manufacturing.